The disclosure relates generally to reducing cache thrashing for counts in hot cache lines.
In contemporary implementations of counts in globally accessible storage of a computer, a problem exists where some of the counts are updated frequently by multiple processors of the computer. That is, each time a processor desires to update a count, that processor must obtain update access to a cache line containing that count. When multiple processors frequently desire to obtain update access to a cache line, that cache line is then frequently passed between processor and cache misses ensue. Cache misses are expensive to resolve in terms of performance of the computer. In addition, cache misses and the resulting performance issues are exacerbated when multiple counts exist within the same cache line.